Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Designs*

In this paper, we describe optimization techniques to minimize important design objectives such as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we employ a new system-performance simulation engine, GTX (GSRC Technology Extrapolation). We concentrate on using accurate models of both circuit and design technology. For example, we take such effects as inductance, repeater staggering, signal line shielding, via parasitics, dynamic delay, and buffer placement uncertainty into account. We examine a typical critical path and apply these optimization techniques using the latest analytical models to determine their potential impact. Results indicate that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues. Also, we demonstrate that optimal wire sizing models need to consider inductive effects and use of the true worst-case capacitive noise switch factor leads to a substantial increase in peak noise compared to a traditional {0,2} bound.